1. Field of the Invention
The present invention relates to data storage devices and, more particularly, to multi-ported data storage devices which support simultaneous read and write operations.
2. Description of the Related Art
Recently, multi-access common storage devices have become the data storage device of choice for processing systems (e.g., microprocessors) having multiple functional units. Multi-access common data storage devices are more commonly known as multi-ported register files or scratch pad registers. Typically, a multi-ported register file is located within the same integrated circuit chip as the processor. The multi-ported register file is normally best used as a temporary, high-speed data storage area.
Although other data storage architectures, such as local memory for each functional unit or shared memory across a bus, could be used to provide on-chip data storage, multi-ported register files offer an architectural solution which is faster and simpler to implement than either shared memory access across a data bus or local memory for each functional unit. Accordingly, multi-ported register files are presently preferred for on-chip, temporary, high-speed data storage.
Multi-ported register files are particularly suited for use as data storage devices for processors having multiple functional units because they enable all the functional units of a processor to simultaneously access the memory cells within the multi-ported file register. Since all the functional units of a processor are permitted to simultaneously access the multi-ported register file, the processor is able to achieve high computation rates.
In general, as the processing power of a processor increases, the number of functional units tends to increase (e.g., superscalar processors). Moreover, the word size also becomes wider and the cycle time tends to decrease as processors become more advanced. As a result, greater demands are placed on the multi-ported register file. To satisfy these ever increasing demands, the multi-ported register file must not only become wider and deeper but also support more ports.
Currently, there exists two known designs for multi-ported register files. One design is based on multiple input/output flip-flop or latch type storage cells. The other design is based on multiple input/output or write/read port memory (SRAM) storage cells.
FIG. 1A illustrates a single memory cell of a latch type multi-ported register file associated with the prior art. Although only a single memory cell is shown, it should be understood that identical memory cells will be present for each bit of each word within the multi-ported register file.
In FIG. 1A, the multi-ported register file includes a memory cell 10 which consists of two cross-coupled inverters 12a and 12b. The inverter 12a has a larger device size than does the inverter 12b. One side of the memory cell 10 contains write ports, while the other side contains read ports. On the side of the read ports, the memory cell 10 is connected to an inverter 13 which serves as a buffering device. Each of the write ports consist of a pass gate 14, and each of the read ports consist of a pass gate 16. The gate terminals of the pass gates 14 are connected to write word lines (WWL), the drain (source) terminals of the pass gates 14 are connected to word bit lines (WBL), and the source (drain) terminals of the pass gates 14 are connected to the write side of the memory cell 10. The gate terminals of the pass gates 16 are connected to read word lines (RWL), the drain (source) terminals of the pass gate 16 are connected to read bit lines (RBL), and the source (drain) terminals of the pass gate 16 are connected to the read side of the memory cell 10 via the inverter 13.
When a bit is to be written into the memory cell 10, the appropriate bit is provided to the pass gate 14 via the corresponding word bit line (WBL), then at the appropriate time the write word line (WWL) will activate the gate terminal of the pass gate 14 so as to pass the bit from the word bit line (WBL) to the memory cell 10 for storage. The read port operates in a similar fashion. The only difference being that when the read word line (RWL) activates the gate terminal of the pass gate 16, the pass gate 16 passes the bit stored in the memory cell 10 (as inverted by the inverter 13) to the read bit line (RBL) of the same read port.
FIG. 1B illustrates a single memory cell of a SRAM based memory type multi-ported register file associated with the prior art. In this case, the inverters 12 are symmetrical. In FIG. 1B, the gate terminals of the pass gates 14 and 16 are connected to a word line (WL). The drain (source) terminals of each of the pass gates 14 are connected to a bit line (BL), and the source (drain) terminals of each of the pass gates 14 are connected to the left side of the memory cell 10. The drain (source) terminals of each of the pass gates 16 are connected to an inverted bit line (BL, and the source (drain) terminals of the pass gate 16 are connected to the right side of the memory cell 10. Hence, the bit line (BL) and the inverted bit line (BL) are shared by the read ports and the write ports. Unlike the latch type design, in the SRAM memory type design data is read from the memory cell by sense amplifiers (not shown) via the pass gates 14 and 16.
The latch design, although useful for a small number of ports, is impracticable for today's multi-ported register files (which would exceed 16 ports in some superscalar designs) because this design requires too much die area and its performance is relatively slow compared to a SRAM based memory cell design.
Although the SRAM based memory cell design offers sufficient speed and utilizes minimal die area, the memory design has a cell stability problem which is difficult to resolve. In multi-ported register files having only a few ports, the cell stability problem is less significant. However, as the number of ports in register files continues to grow geometrically, cell stability becomes a serious concern that cannot be ignored for memory designs.
Cell stability during read operations is a major consideration in the design of SRAM based memory type multi-ported register files. The stability of memory cells are at risk during read operations because bit lines could potentially overwrite a stored bit in the memory cell during read operations if both read bit line levels are not high enough prior to access. When the memory design is used for the multi-ported register file, cell stability is of particular concern because the pull down to pass gate size ratio (a leading indicator for cell stability) will be different depending on how many ports are accessed at the same time. If the pull down to pass gate size ratio is optimized for single port access, it could cause cell instability when multiple ports are accessed. However, if it is optimized for multiple port access, the access time to the memory cells is slowed significantly. Capacitive cross coupling between bit lines and multiple port accessing can also degrade cell stability.
Access time to the memory cells is also a major consideration in the design of multi-ported register files. Simultaneous multiple port accesses will slow access time in the conventional latch and memory type multi-ported register files. In addition, in the conventional designs, the access time varies with the number of ports which simultaneously access a memory cell.
One known solution to the cell stability problem has been used with a multi-ported register file having 17 ports to ensure sufficient bit line precharge levels. This solution has the disadvantages of requiring additional precharge pulse generation circuitry which will generate a lot of noise that further complicates the cell stability problem. This solution is more fully described in Jolly, "A 9-ns, 1.4 Gigabyte/s, 17-Ported CMOS Register File," IEEE Journal of Solid-State Circuits, Vol. 26, No. 10, October 1991, which is hereby incorporated by reference.
Another known solution uses tri-state buffers (each of which is composed of several transistors) to buffer and completely isolate bit lines. An example of this approach is described in WIPO international publication number WO 92/08230, entitled "High-speed Five-ported Register File having Simultaneous Read and Write Capability and High Tolerance to Clock Skew" and published on May 14, 1992. This solution, however, was used in a latch design and required too much die area to form all the tri-state buffers included in the design. Namely, using tri-state buffers to buffer and completely isolate bit lines requires an excessive number of transistors which are not required for proper performance. These additional transistors take up precious die space and reduce the speed of the register file.
Thus, there is a need for a multi-ported register file design which eliminates the cell stability and access timing problems, yet utilizes only a minimal amount of additional die area and continues to satisfy the speed requirements of processors.